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By George E Frost

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Indicates JEDEC Registered Data. 1 Figure 12. 0 Figure 13. 8 20 Figure 11. DC Current Gain VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS) VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 10. 0 IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS) Figure 14. “On” Voltage Figure 15. 0 10 20 30 50 70 100 VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS) Figure 16. Forward Bias Safe Operating Area There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown.

The transistor must not be subjected to greater dissipation than the curves indicate. The data of Figure 7 is based on TJ(pk) = 200_C; TC is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided TJ(pk) < 200_C. At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown. POWER DERATING FACTOR (%) 100 80 60 THERMAL DERATING 40 20 0 0 40 80 120 TC, CASE TEMPERATURE (°C) Figure 17.

1) Pulse Test: Pulse Width = 5 ms, Duty Cycle v 10%. Preferred devices are ON Semiconductor recommended choices for future use and best overall value.  Semiconductor Components Industries, LLC, 2001 March, 2001 – Rev. 5 — Adc DYNAMIC CHARACTERISTICS SECOND BREAKDOWN CHARACTERISTICS Second Breakdown Collector Current with Base Forward Biased t = 1 s (non–repetitive), VCE = 100 V, See Figure 12 (2) Pulse Test: Pulse Width = 300 µs, Duty Cycle v 2%. *Indicates JEDEC Registered Data. 1 Figure 12.

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